In some approaches the floorplan may be a partition of the whole chip area into axis aligned rectangles to be occupied by IC blocks. This partition is subject to various constraints and requirements of optimization: block area, aspect ratios, estimated total measure of interconnects, etc.
microelectronics an integrated approach
Finding good floorplans has been a research area in combinatorial optimization. Most of the problems related to finding optimal floorplans are NP-hard, i.e., require vast computational resources. Therefore, the most common approach is to use various optimization heuristics for finding good solutions.
IN3, a statewide applied research institute, is composed of top leaders from academia, government and industry. It seeks to solve real-world problems that impact industry and the U.S. Department of Defense in a faster, more efficient and cost-effective way. Currently, it is engaged in projects focused on trusted microelectronics, hypersonics, electro-optics and target machine learning.
David Crandall: Our role in this project is to use computer vision and machine learning techniques to help ensure the integrity of the supply chain around microelectronics. One way is to use computer vision to inspect integrated circuits to see whether there is something suspicious that might suggest they are damaged or counterfeit.
DC: My understanding is that current approaches to detecting counterfeit devices are either limited in their accuracy or must be done by hand, which is expensive and time-consuming. If we can create new automated techniques that could complement or improve these approaches, we can potentially ensure that more devices are inspected.
IN3 encourages Indiana University innovators and researchers who have ideas, research or projects that fit the focus areas of electro-optics, hypersonics, trusted microelectronics and target machine learning to make contact via innovations@in3indiana.com.
Quilt Packaging offers world-record interchip interconnect performance. IIC has demonstrated interchip insertion losses of less than 1 dB all the way from DC to 220 GHz with no resonances. Also, QP nodules have been shown to pass several amps without degradation. Pull-tests show that QP nodules are individually as strong as, or stronger than, bond wires, but work in tandem to make strong and reliable systems. Easily-accomplished deep submicron chip-to-chip registration allows applications in RF, microwave, digital, power, biomedical and integrated-optical systems.
Game changing performance improvements are enabled by QP at costs comparable to or lower than competing integration approaches. Revolutionary advances are currently underway in microwave/RF, large format arrays, power electronics and more.
The center conducts fundamental research in three technical areas meant to establish the foundation for future secure and trusted semiconductor/ microelectronics technologies: (1) new substrates, synthesis, and fabrication, (2) new computing paradigms and architectures, and (3) integrated sensing, edge computing, and secure communications.
By standardizing processes and technologies across multiple sites, an integrated manufacturing approach can bring trust and agility to mission-critical programs. From chip-scale microelectronics to system-scale radio frequency (RF) integration, Mercury invests in the most advanced production technologies.
From silicon to subsystems, we leverage the latest automated manufacturing technologies to help customers scale mission-critical programs from initial engineering samples to full-rate production. With a trusted supply chain, secure processes and space-qualified microelectronics, we have the proven experience to deliver mission success.
Our integrated SMT lines utilize the most advanced equipment to rapidly assemble high-performance RF and digital processing boards while minimizing product variation. Whether for artificial intelligence (AI) processing modules or integrated RF solutions, Mercury has deployed the most advanced manufacturing processes and systems to deliver reliable, proven results.
Mercury is an accredited Defense Microelectronics Activity (DMEA) "trusted supplier" and a Trusted Electronic Designer, Fabricator, and Assembler with IPC-1791-certified facilities. Manufacturing logic components ranging from DMEA microelectronics to motherboards, our facilities deliver full supply chain traceability through management procedures including audits and supply scorecards.
N2 - This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture, In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field programmable gate arrays using their Supercell approach, is studied. Architectural constraints to implement fault tolerant circuit design in this architecture are discussed. Some modifications of its basic Structure, such as the integration of circuitry for error correction and scan path, to enhance fault tolerant circuits design are introduced and are compared to the Supercell approach.
AB - This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture, In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field programmable gate arrays using their Supercell approach, is studied. Architectural constraints to implement fault tolerant circuit design in this architecture are discussed. Some modifications of its basic Structure, such as the integration of circuitry for error correction and scan path, to enhance fault tolerant circuits design are introduced and are compared to the Supercell approach.
OBJECTIVE: Support the development of radiation susceptibility analysis and prediction capabilities in defense systems to reduce the design risks, schedules and overhead while resulting in significant savings in costs and high reliability radiation tolerant microelectronics for DoD missions.
DESCRIPTION: Reliable radiation tolerant microelectronics in modern technology nodes is critical to DoD missions. Development, however, is challenging, costly and requires long design cycles. The effectiveness of the radiation mitigation capabilities is only assessed after a device is manufactured adding significant risk to system development. As the vulnerability of microelectronics to radiation effects increases with modern technology, so does the challenge of implementing radiation tolerance in a strategic manner. Significant feature overhead in both the microelectronic device and supporting system is often necessary; furthermore, there is a limiting effect on the potential performance of a device relative to the capabilities of the technology used for implementation. There is a critical need for efficient approaches/capabilities for radiation susceptibility analysis and prediction that would enable developers to apply the appropriate amount of radiation mitigation to a design and, more importantly, help predict the resiliency of hardened microelectronics prior to device manufacturing.
Assessing radiation effects in microelectronics prior to fabrication currently broadly falls in to two approaches: physics based modeling simulations and fault injection simulations. Neither approach is suitable for assessing or predicting radiation effects on the scale of an entire microelectronics chip design. With both approaches, it is necessary to fabricate and test a design in a radiation environment to assess the performance of any implemented mitigation strategies. Furthermore, these approaches lack a direct means for reliable, direct correlation of the resiliency performance for a fabricated design to the effectiveness and contribution of specific mitigation implementations applied to specific regions of said design.
Of particular interest to this solicitation are new and efficient approaches capable of providing radiation susceptibility analysis and prediction for an entire microelectronic chip while using reasonable computing resources and within acceptable processing delays.
PHASE II: Demonstrate a prototype level of a radiation susceptibility analysis and prediction compute platform capable of processing a full chip design. The outcome of Phase would include 1) Optimization of the analytical assessment classifier built in Phase I to increase and optimize processing throughput, 2) Development of abstraction modeling coupons to provide the necessary parameterization, 3) Development of the technology abstraction library and strike model library, 4) Optimization of the strike model library developed in Phase I by leveraging the feedback data provided with testing the abstraction modeling coupons and 5) Development of a susceptibility classifier and integration of a radiation susceptibility analysis and predictor accelerator into a prototype level and fully integrated. The Radiation susceptibility results of a full chip design will be compared to the results obtained by the radiation susceptibility analysis and prediction platform.
The development of semiconductor lasers is a good illustration of the major progress that has been recorded in terms of basic concepts and the mastery of manufacturing processes. Owing to their maturity and diversity, laser diodes are becoming highly popular in a number of applications ranging from the general public to leading edge industrial processes. Nevertheless, courses derived from this area of microelectronics are still too few and far between in postgraduate studies and remain, on the whole, essentially theoretical.
Spin torque oscillators (STOs) are microwave oscillators with an attractive blend of features, including a more-than-octave tunability, GHz operating frequencies, nanoscale size, nanosecond switching speed and full compatibility with CMOS technology. Over the past decade, STOs' physical phenomena have been explored to a greater extent, their performance has been further improved, and STOs have already shown great potential for a wide range of applications, from microwave sources and detectors to neuromorphic computing. This thesis is devoted to promoting the STO technology towards its applications, by means of implementing the STO's electrical model, dedicated CMOS integrated circuits (ICs), and STO-CMOS IC integration. 2ff7e9595c
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